ASU Electronic Theses and Dissertations

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Date Range
2012 2017

Wireless video sensor networks has been examined and evaluated for wide range of applications comprising of video surveillance, video tracking, computer vision, remote live video and control. The reason behind importance of sensor nodes is its ease of implementation, ability to operate in adverse environments, easy to troubleshoot, repair and the high performance level. The biggest challenges with the architectural design of wireless video sensor networks are power consumption, node failure, throughput, durability and scalability. The whole project here is to create a gateway node to integrate between "Internet of things" framework and wireless sensor network. Our Flexi-Wireless Video Sensor ...

Contributors
Shah, Tejas, Reisslein, Martin, Kitchen, Jennifer, et al.
Created Date
2014

Several state of the art, monitoring and control systems, such as DC motor controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as ...

Contributors
Thirunakkarasu, Shankar, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2014

Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management ...

Contributors
Malladi, Venkata Naga Koushik, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2015

In-band full-duplex relays are envisioned as promising solution to increase the throughput of next generation wireless communications. Full-duplex relays, being able to transmit and receive at same carrier frequency, offers increased spectral efficiency compared to half-duplex relays that transmit and receive at different frequencies or times. The practical implementation of full-duplex relays is limited by the strong self-interference caused by the coupling of relay's own transit signals to its desired received signals. Several techniques have been proposed in literature to mitigate the relay self-interference. In this thesis, the performance of in-band full-duplex multiple-input multiple-output (MIMO) relays is considered in the ...

Contributors
Sekhar, Kishore Kumar Kumar, Bliss, Daniel W, Kitchen, Jennifer, et al.
Created Date
2014

Dissertation/Thesis

Contributors
Javidahmadabadi, Mahdi, Kitchen, Jennifer, Bakkaloglu, Bertan, et al.
Created Date
2015

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time. Dissertation/Thesis

Contributors
Kim, Kibeom, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2013

This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design ...

Contributors
Spivey, Erin Leason, Aberle, James, Kitchen, Jennifer, et al.
Created Date
2012

Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog ...

Contributors
Nazari, Ali, Barnaby, Hugh James, Jalali-Farahani, Bahar, et al.
Created Date
2017

Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented ...

Contributors
Venkatasubramanian, Ramachandran, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2016

RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). ...

Contributors
Gangula, Sudheer Kumar Reddy, Kitchen, Jennifer, Ozev, Sule, et al.
Created Date
2015

This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries.

For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.