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ASU Electronic Theses and Dissertations


This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.


Date Range
2013 2018


In this work, the development of a novel and a truly in-shoe force measurement system is reported. The device consists of a shoe insole with six thin film piezoresistive sensors and the main circuit board. The piezoresistive sensors are used for the measurement of plantar pressure during daily human activities. The motion sensor mounted on the main circuit board captures kinematic data. In addition, the main circuit board is responsible for the wireless transmission of the data from all the sensors in real-time using BLE protocol. It is housed within the midsole of the shoe, under the medial arch of ...

Contributors
Badarinath, Abhishek, Kiaei, Sayfe, Bakkaloglu, Bertan, et al.
Created Date
2018

Traditional wireless communication systems operate in duplexed modes i.e. using time division duplexing or frequency division duplexing. These methods can respectively emulate full duplex mode operation or realize full duplex mode operation with decreased spectral efficiency. This thesis presents a novel method of achieving full duplex operation by actively cancelling out the transmitted signal in pseudo-real time. With appropriate hardware, the algorithms and techniques used in this work can be implemented in real time without any knowledge of the channel or any training sequence. Convergence times of down to 1 ms can be achieved which is adequate for the coherence ...

Contributors
Avasarala, Sanjay, Kiaei, Sayfe, Kitchen, Jennifer, et al.
Created Date
2016

High-efficiency DC-DC converters make up one of the important blocks of state-of-the-art power supplies. The trend toward high level of transistor integration has caused load current demands to grow significantly. Supplying high output current and minimizing output current ripple has been a driving force behind the evolution of Multi-phase topologies. Ability to supply large output current with improved efficiency, reduction in the size of filter components, improved transient response make multi-phase topologies a preferred choice for low voltage-high current applications. Current sensing capability inside a system is much sought after for applications which include Peak-current mode control, Current limiting, Overload ...

Contributors
Burli, Venkatesh, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2017

High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling ...

Contributors
Jankunas, Benjamin, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2014

Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of ...

Contributors
Kumar, Amit, Bakkaloglu, Bertan, Song, Hongjiang, et al.
Created Date
2013

Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios ...

Contributors
Magod Ramakrishna, Raveesh, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2014

A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final ...

Contributors
Sun, Ming, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2017

Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply. This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random ...

Contributors
Bakliwal, Priyanka, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2015

In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any ...

Contributors
Schmelter, Brooke, Bakkaloglu, Bertan, Ogras, Umit, et al.
Created Date
2017

The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system. Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and ...

Contributors
Ayati, Seyyed Amir, Kiaei, Sayfe, Bakkaloglu, Bertan, et al.
Created Date
2017