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ASU Electronic Theses and Dissertations


This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.


Graphs are one of the key data structures for many real-world computing applica- tions such as machine learning, social networks, genomics etc. The main challenges of graph processing include diculty in parallelizing the workload that results in work- load imbalance, poor memory locality and very large number of memory accesses. This causes large-scale graph processing to be very expensive. This thesis presents implementation of a select set of graph kernels on a multi-core architecture, Transmuter. The kernels are Breadth-First Search (BFS), Page Rank (PR), and Single Source Shortest Path (SSSP). Transmuter is a multi-tiled architec- ture with 4 tiles and …

Contributors
RENGANATHAN, SRINIDHI, CHAKRABARTI, CHAITALI, Shrivastava, Aviral, et al.
Created Date
2019

Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description …

Contributors
Sharma, Abhishek, Clark, Lawrence, Holbert, Keith, et al.
Created Date
2011