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ASU Electronic Theses and Dissertations


This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.


Contributor
Language
  • English
Subject
Date Range
2012 2019


Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag ing systems. Performance of ROICs affect the quality of images obtained from IR imaging systems. Contemporary infrared imaging applications demand ROICs that can support large dynamic range, high frame rate, high output data rate, at low cost, size and power. Some of these applications are military surveillance, remote sensing in space and earth science missions and medical diagnosis. This work focuses on developing a ROIC unit cell prototype for National Aeronautics and Space Ad ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These space applications also demand high sensitivity, longer integration times(large well …

Contributors
Praveen, Subramanya Chilukuri, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2019

Traditional wireless communication systems operate in duplexed modes i.e. using time division duplexing or frequency division duplexing. These methods can respectively emulate full duplex mode operation or realize full duplex mode operation with decreased spectral efficiency. This thesis presents a novel method of achieving full duplex operation by actively cancelling out the transmitted signal in pseudo-real time. With appropriate hardware, the algorithms and techniques used in this work can be implemented in real time without any knowledge of the channel or any training sequence. Convergence times of down to 1 ms can be achieved which is adequate for the coherence …

Contributors
Avasarala, Sanjay, Kiaei, Sayfe, Kitchen, Jennifer, et al.
Created Date
2016

High-efficiency DC-DC converters make up one of the important blocks of state-of-the-art power supplies. The trend toward high level of transistor integration has caused load current demands to grow significantly. Supplying high output current and minimizing output current ripple has been a driving force behind the evolution of Multi-phase topologies. Ability to supply large output current with improved efficiency, reduction in the size of filter components, improved transient response make multi-phase topologies a preferred choice for low voltage-high current applications. Current sensing capability inside a system is much sought after for applications which include Peak-current mode control, Current limiting, Overload …

Contributors
Burli, Venkatesh, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2017

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below: 1) A transformer-based power combiner architecture for out-phasing transmitters 2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA) 3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power …

Contributors
Moallemi, Soroush, Kitchen, Jennifer, Kiaei, Sayfe, et al.
Created Date
2019

There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice …

Contributors
HabibiMehr, Payam, Thornton, Trevor John, Bakkaloglu, Bertan, et al.
Created Date
2019

High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling …

Contributors
Jankunas, Benjamin, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2014

Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of …

Contributors
Kumar, Amit, Bakkaloglu, Bertan, Song, Hongjiang, et al.
Created Date
2013

Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios …

Contributors
Magod Ramakrishna, Raveesh, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2014

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time. Dissertation/Thesis

Contributors
Kim, Kibeom, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2013

A 4-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and digital current sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line based PWM generator, without affecting the phase synchronization timing sequence. In light load conditions, individual converter phases can be disabled, and the final …

Contributors
Sun, Ming, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2017