Skip to main content

ASU Electronic Theses and Dissertations


This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.


Date Range
2014 2019


Switch mode DC/DC converters are suited for battery powered applications, due to their high efficiency, which help in conserving the battery lifetime. Fixed Frequency PWM based converters, which are generally used for these applications offer good voltage regulation, low ripple and excellent efficiency at high load currents. However at light load currents, fixed frequency PWM converters suffer from poor efficiencies The PFM control offers higher efficiency at light loads at the cost of a higher ripple. The PWM has a poor efficiency at light loads but good voltage ripple characteristics, due to a high switching frequency. To get the best …

Contributors
Vivek, Parasuram, Bakkaloglu, Bertan, Ogras, Umit, et al.
Created Date
2014

ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations …

Contributors
Kumar, Sushil, Clark, Lawrence, Bakkaloglu, Bertan, et al.
Created Date
2014

Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics …

Contributors
Yang, Chengen, Chakrabarti, Chaitali, Cao, Yu, et al.
Created Date
2014

The research objective is fully differential op-amp with common mode feedback, which are applied in filter, band gap, Analog Digital Converter (ADC) and so on as a fundamental component in analog circuit. Having modeled various defect and analyzed corresponding probability, defect library could be built after reduced defect simulation.Based on the resolution of microscope scan tool, all these defects are categorized into four groups of defects by both function and location, bias circuit defect, first stage amplifier defect, output stage defect and common mode feedback defect, separately. Each fault result is attributed to one of these four region defects.Therefore, analog …

Contributors
Lu, Zhijian, Ozev, Sule, Kiaei, Sayfe, et al.
Created Date
2014

Switching Converters (SC) are an excellent choice for hand held devices due to their high power conversion efficiency. However, they suffer from two major drawbacks. The first drawback is that their dynamic response is sensitive to variations in inductor (L) and capacitor (C) values. A cost effective solution is implemented by designing a programmable digital controller. Despite variations in L and C values, the target dynamic response can be achieved by computing and programming the filter coefficients for a particular L and C. Besides, digital controllers have higher immunity to environmental changes such as temperature and aging of components. The …

Contributors
Mumma Reddy, Abhiram, Bakkaloglu, Bertan, Ogras, Umit, et al.
Created Date
2014

Register file (RF) memory is important in low power system on chip (SOC) due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height. Dissertation/Thesis

Contributors
Vashishtha, Vinay, Clark, Lawrence T., Seo, Jae-sun, et al.
Created Date
2014

Three dimensional (3-D) ultrasound is safe, inexpensive, and has been shown to drastically improve system ease-of-use, diagnostic efficiency, and patient throughput. However, its high computational complexity and resulting high power consumption has precluded its use in hand-held applications. In this dissertation, algorithm-architecture co-design techniques that aim to make hand-held 3-D ultrasound a reality are presented. First, image enhancement methods to improve signal-to-noise ratio (SNR) are proposed. These include virtual source firing techniques and a low overhead digital front-end architecture using orthogonal chirps and orthogonal Golay codes. Second, algorithm-architecture co-design techniques to reduce the power consumption of 3-D SAU imaging systems …

Contributors
Yang, Ming, Chakrabarti, Chaitali, Papandreou-Suppappola, Antonia, et al.
Created Date
2015

Power Management circuits are employed in almost all electronic equipment and they have energy storage elements (capacitors and inductors) as building blocks along with other active circuitry. Power management circuits employ feedback to achieve good load and line regulation. The feedback loop is designed at an operating point and component values are chosen to meet that design requirements. But the capacitors and inductors are subject to variations due to temperature, aging and load stress. Due to these variations, the feedback loop can cross its robustness margins and can lead to degraded performance and potential instability. Another issue in power management …

Contributors
Malladi, Venkata Naga Koushik, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2015

Clock generation and distribution are essential to CMOS microchips, providing synchronization to external devices and between internal sequential logic. Clocks in microprocessors are highly vulnerable to single event effects and designing reliable energy efficient clock networks for mission critical applications is a major challenge. This dissertation studies the basics of radiation hardening, essentials of clock design and impact of particle strikes on clocks in detail and presents design techniques for hardening complete clock systems in digital ICs. Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse …

Contributors
Chellappa, Srivatsan, Clark, Lawrence T, Holbert, Keith E, et al.
Created Date
2015

RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). …

Contributors
Gangula, Sudheer Kumar Reddy, Kitchen, Jennifer, Ozev, Sule, et al.
Created Date
2015

ABSTRACT Designers creating the next generation remote sensing enabled smart devices need to overcome the challenges of prevailing ventures including time to market and expense. To reduce the time and effort involved in initial prototyping, a good reference design is often desired and warranted. This paper provides the necessary reference materials for Designers to implement a wireless solution efficiently and effectively. This document is intended for users with limited Bluetooth technology experience. Many sensing-enabled devices require a ‘hard-wire’ or cable link to a host monitoring system. This can limit the potential for product advancements by anchoring the system to a …

Contributors
Hughes, Clinton Francis, Blain Christen, Jennifer, Ozev, Sule, et al.
Created Date
2015

Object tracking is an important topic in multimedia, particularly in applications such as teleconferencing, surveillance and human-computer interface. Its goal is to determine the position of objects in images continuously and reliably. The key steps involved in object tracking are foreground detection to detect moving objects, clustering to enable representation of an object by its centroid, and tracking the centroids to determine the motion parameters. In this thesis, a low cost object tracking system is implemented on a hardware accelerator that is a warp based processor for SIMD/Vector style computations. First, the different foreground detection techniques are explored to figure …

Contributors
Sasikumar, Asha, Chakrabarti, Chaitali, Ogras, Umit, et al.
Created Date
2015

Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope …

Contributors
Jeong, Jae Woong, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2015

Historically, wireless communication devices have been developed to process one specific waveform. In contrast, a modern cellular phone supports multiple waveforms corresponding to LTE, WCDMA(3G) and 2G standards. The selection of the network is controlled by software running on a general purpose processor, not by the user. Now, instead of selecting from a set of complete radios as in software controlled radio, what if the software could select the building blocks based on the user needs. This is the new software-defined flexible radio which would enable users to construct wireless systems that fit their needs, rather than forcing to use …

Contributors
Chagari, Vamsi Reddy, Chakrabarti, Chaitali, Lee, Hyunseok, et al.
Created Date
2016

Coarse-grained Reconfigurable Arrays (CGRAs) are promising accelerators capable of accelerating even non-parallel loops and loops with low trip-counts. One challenge in compiling for CGRAs is to manage both recurring and nonrecurring variables in the register file (RF) of the CGRA. Although prior works have managed recurring variables via rotating RF, they access the nonrecurring variables through either a global RF or from a constant memory. The former does not scale well, and the latter degrades the mapping quality. This work proposes a hardware-software codesign approach in order to manage all the variables in a local nonrotating RF. Hardware provides modulo …

Contributors
Dave, Shail, Shrivastava, Aviral, Ren, Fengbo, et al.
Created Date
2016

Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power, better performance and lower hardware cost. First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 …

Contributors
Chen, Hsing-Min, Chakrabarti, Chaitali, Mudge, Trevor, et al.
Created Date
2017

Accessibility to the internal nodes of an analog/mixed-signal circuit while testing is extremely difficult. Furthermore, with technology scaling, the effect of process variations becomes more pronounced which in turn effects the test time, test cost, and die yield. As devices become more unreliable, the probability of failure of a die increases, yield decreases affecting the quality of test and cost.Therefore, test time minimization and test cost reduction are important. Moreover, process variations can affect the performance of analog/mixed circuits. Therefore, the performance of a System On-Chip(SoC) which tends to integrate multiple band gap reference circuits (BGRs) is effected due to …

Contributors
Ravouri, Yestina, Ozev, Sule, Ogras, Umit, et al.
Created Date
2017

This thesis presents a power harvesting system combining energy from sub-cells of multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A modified hill-climbing algorithm is implemented to achieve maximum power point tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of 65mW. Measured results show that …

Contributors
Peng, Qirong, Kiaei, Sayfe, Bakkaloglu, Bertan, et al.
Created Date
2017

Caches pose a serious limitation in scaling many-core architectures since the demand of area and power for maintaining cache coherence increases rapidly with the number of cores. Scratch-Pad Memories (SPMs) provide a cheaper and lower power alternative that can be used to build a more scalable many-core architecture. The trade-off of substituting SPMs for caches is however that the data must be explicitly managed in software. Heap management on SPM poses a major challenge due to the highly dynamic nature of of heap data access. Most existing heap management techniques implement a software caching scheme on SPM, emulating the behavior …

Contributors
Lin, Jinn-Pean, Shrivastava, Aviral, Ren, Fengbo, et al.
Created Date
2017

In this work, a 12-bit ADC with three types of calibration is proposed for high speed security applications as well as a precision application. This converter performs for both applications because it satisfies all the necessary specifications such as minimal device mismatch and offset, programmability to decrease aging effects, high SNR for increased ENOB and fast conversion rate. The designed converter implements three types of calibration necessary for offset and gain error, including: a correlated double sampling integrator used in the first stage of the ADC, a power up auto zero technique implemented in the digital code to store any …

Contributors
Schmelter, Brooke, Bakkaloglu, Bertan, Ogras, Umit, et al.
Created Date
2017

Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST …

Contributors
Ozel, Muhlis Kenan, Bakkaloglu, Bertan, Ozev, Sule, et al.
Created Date
2017

Designers employ a variety of modeling theories and methodologies to create functional models of discrete network systems. These dynamical models are evaluated using verification and validation techniques throughout incremental design stages. Models created for these systems should directly represent their growing complexity with respect to composition and heterogeneity. Similar to software engineering practices, incremental model design is required for complex system design. As a result, models at early increments are significantly simpler relative to real systems. While experimenting (verification or validation) on models at early increments are computationally less demanding, the results of these experiments are less trustworthy and less …

Contributors
Gholami, Soroosh, Sarjoughian, Hessam S, Fainekos, Georgios, et al.
Created Date
2017

Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on the devices. In this dissertation, firstly, a methodology for analyzing the performance degradation of RF circuits caused …

Contributors
Chang, Doo Hwang, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2017

Software-defined radio provides users with a low-cost and flexible platform for implementing and studying advanced communications and remote sensing applications. Two such applications include unmanned aerial system-to-ground communications channel and joint sensing and communication systems. In this work, these applications are studied. In the first part, unmanned aerial system-to-ground communications channel models are derived from empirical data collected from software-defined radio transceivers in residential and mountainous desert environments using a small (< 20 kg) unmanned aerial system during low-altitude flight (< 130 m). The Kullback-Leibler divergence measure was employed to characterize model mismatch from the empirical data. Using this measure …

Contributors
Gutierrez, Richard, Bliss, Daniel W, Papandreou-Suppappola, Antonia, et al.
Created Date
2018

Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain …

Contributors
Lim, Chai Yong, Kiaei, Sayfe, Bakkaloglu, Bertan, et al.
Created Date
2018

As integrated technologies are scaling down, there is an increasing trend in the process,voltage and temperature (PVT) variations of highly integrated RF systems. Accounting for these variations during the design phase requires tremendous amount of time for prediction of RF performance and optimizing it accordingly. Thus, there is an increasing gap between the need to relax the RF performance requirements at the design phase for rapid development and the need to provide high performance and low cost RF circuits that function with PVT variations. No matter how care- fully designed, RF integrated circuits (ICs) manufactured with advanced technology nodes necessitate …

Contributors
Shafiee, Maryam, Ozev, Sule, Diaz, Rodolfo, et al.
Created Date
2018

This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal …

Contributors
EROL, OSMAN EMIR, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2018

Medical ultrasound imaging is widely used today because of it being non-invasive and cost-effective. Flow estimation helps in accurate diagnosis of vascular diseases and adds an important dimension to medical ultrasound imaging. Traditionally flow estimation is done using Doppler-based methods which only estimate velocity in the beam direction. Thus when blood vessels are close to being orthogonal to the beam direction, there are large errors in the estimation results. In this dissertation, a low cost blood flow estimation method that does not have the angle dependency of Doppler-based methods, is presented. First, a velocity estimator based on speckle tracking and …

Contributors
WEI, SIYUAN, Chakrabarti, Chaitali, Papandreou-Suppappola, Antonia, et al.
Created Date
2018

While machine/deep learning algorithms have been successfully used in many practical applications including object detection and image/video classification, accurate, fast, and low-power hardware implementations of such algorithms are still a challenging task, especially for mobile systems such as Internet of Things, autonomous vehicles, and smart drones. This work presents an energy-efficient programmable application-specific integrated circuit (ASIC) accelerator for object detection. The proposed ASIC supports multi-class (face/traffic sign/car license plate/pedestrian), many-object (up to 50) in one image with different sizes (6 down-/11 up-scaling), and high accuracy (87% for face detection datasets). The proposed accelerator is composed of an integral channel detector …

Contributors
Kim, Minkyu, Seo, Jae-sun, Cao, Yu Kevin, et al.
Created Date
2019

With the exponential growth in video content over the period of the last few years, analysis of videos is becoming more crucial for many applications such as self-driving cars, healthcare, and traffic management. Most of these video analysis application uses deep learning algorithms such as convolution neural networks (CNN) because of their high accuracy in object detection. Thus enhancing the performance of CNN models become crucial for video analysis. CNN models are computationally-expensive operations and often require high-end graphics processing units (GPUs) for acceleration. However, for real-time applications in an energy-thermal constrained environment such as traffic management, GPUs are less …

Contributors
Dua, Akshay, Ren, Fengbo, Ogras, Umit, et al.
Created Date
2019

Ultrasound B-mode imaging is an increasingly significant medical imaging modality for clinical applications. Compared to other imaging modalities like computed tomography (CT) or magnetic resonance imaging (MRI), ultrasound imaging has the advantage of being safe, inexpensive, and portable. While two dimensional (2-D) ultrasound imaging is very popular, three dimensional (3-D) ultrasound imaging provides distinct advantages over its 2-D counterpart by providing volumetric imaging, which leads to more accurate analysis of tumor and cysts. However, the amount of received data at the front-end of 3-D system is extremely large, making it impractical for power-constrained portable systems. In this thesis, algorithm and …

Contributors
Zhou, Jian, Chakrabarti, Chaitali, Papandreou-Suppappola, Antonia, et al.
Created Date
2019

Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, a realistic finFET based predictive process design kit (PDK) that supports investigation into both circuit and physical design, encompassing all aspects of digital design, for academic use has been unavailable. While the finFET based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification (LVS) and parasitic extraction at the time [3][4]. Consequently, the only …

Contributors
Vashishtha, Vinay, Clark, Lawrence T., Allee, David R., et al.
Created Date
2019