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ASU Electronic Theses and Dissertations


This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.

In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.

Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.


Contributor
Date Range
2010 2019


An investigation of phase noise in amplifier and voltage-controller oscillator (VCO) circuits was conducted to show that active direct-current (DC) bias techniques exhibit lower phase noise performance than traditional resistive DC bias techniques. Low-frequency high-gain amplifiers like those found in audio applications exhibit much better 1/f phase noise performance and can be used to bias amplifier or VCO circuits that work at much higher frequencies to reduce the phase modulation caused by higher frequency devices. An improvement in single-side-band (SSB) phase noise of 15 dB at offset frequencies less than 50 KHz was simulated and measured. Residual phase noise of …

Contributors
Baldwin, Jeremy Bart, Aberle, James, Bakkaloglu, Bertan, et al.
Created Date
2010

In this thesis two methodologies have been proposed for evaluating the fault response of analog/RF circuits. These proposed approaches are used to evaluate the response of the faulty circuit in terms of specifications/measurements. Faulty response can be used to evaluate important test metrics like fail probability, fault coverage and yield coverage of given measurements under process variations. Once the models for faulty and fault free circuit are generated, one needs to perform Monte Carlo sampling (as opposed to Monte Carlo simulations) to compute these statistical parameters with high accuracy. The first method is based on adaptively determining the order of …

Contributors
Subrahmaniyan Radhakrishnan, Gurusubrahmaniyan, Ozev, Sule, Blain Christen, Jennifer, et al.
Created Date
2010

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA …

Contributors
Yeom, Hyunsoo, Bakkaloglu, Bertan, Kiaei, Sayfe, et al.
Created Date
2011

Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. …

Contributors
Lee, Junghan, Bakkaloglu, Bertan, Kiaei, Sayfe, et al.
Created Date
2011

ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF …

Contributors
Sreenivassan, Aiswariya, Ozev, Sule, Kiaei, Sayfe, et al.
Created Date
2011

Voltage Control Oscillator (VCO) is one of the most critical blocks in Phase Lock Loops (PLLs). LC-tank VCOs have a superior phase noise performance, however they require bulky passive resonators and often calibration architectures to overcome their limited tuning range. Ring oscillator (RO) based VCOs are attractive for digital technology applications owing to their ease of integration, small die area and scalability in deep submicron processes. However, due to their supply sensitivity and poor phase noise performance, they have limited use in applications demanding low phase noise floor, such as wireless or optical transceivers. Particularly, out-of-band phase noise of RO-based …

Contributors
Min, Seungkee, Kiaei, Sayfe, Bakkaloglu, Bertan, et al.
Created Date
2011

Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity …

Contributors
Liu, Tao, Bakkaloglu, Bertan, Bakkaloglu, Bertan, et al.
Created Date
2011

In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral …

Contributors
Goyal, Nitin, Ozev, Sule, Duman, Tolga, et al.
Created Date
2011

The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried …

Contributors
Guerra, Diego, Saraniti, Marco, Saraniti, Marco, et al.
Created Date
2011

Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities …

Contributors
Zazzera, Joshua, Bakkaloglu, Bertan, Bakkaloglu, Bertan, et al.
Created Date
2012

Power management plays a very important role in the current electronics industry. Battery powered and handheld applications require novel power management techniques to extend the battery life. Most systems have multiple voltage regulators to provide power sources to the different circuit blocks and/or sub-systems. Some of these voltage regulators are low dropout regulators (LDOs) which typically require output capacitors in the range of 1's to 10's of µF. The necessity of output capacitors occupies valuable board space and can add additional integrated circuit (IC) pin count. A high IC pin count can restrict LDOs for system-on-chip (SoC) solutions. The presented …

Contributors
Topp, Matthew, Bakkaloglu, Bertan, Thornton, Trevor, et al.
Created Date
2012

Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output …

Contributors
Byregowda, Srinath, Ozev, Sule, Cao, Yu, et al.
Created Date
2012

Micro-Electro Mechanical System (MEMS) is the micro-scale technology applying on various fields. Traditional testing strategy of MEMS requires physical stimulus, which leads to high cost specified equipment. Also there are a large number of wafer-level measurements for MEMS. A method of estimation calibration coefficient only by electrical stimulus based wafer level measurements is included in the thesis. Moreover, a statistical technique is introduced that can reduce the number of wafer level measurements, meanwhile obtaining an accurate estimate of unmeasured parameters. To improve estimation accuracy, outlier analysis is the effective technique and merged in the test flow. Besides, an algorithm for …

Contributors
Deng, Lingfei, Ozev, Sule, Yu, Hongyu, et al.
Created Date
2012

Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to …

Contributors
Chakraborty, Bijeta, Bakkaloglu, Bertan, Garrity, Douglas, et al.
Created Date
2012

This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design …

Contributors
Spivey, Erin Leason, Aberle, James, Kitchen, Jennifer, et al.
Created Date
2012

Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals …

Contributors
Yilmaz, Ender, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2012

Mobile electronic devices such as smart phones, netbooks and tablets have seen increasing demand in recent years, and so has the need for efficient, responsive and small power management solutions that are integrated into these devices. Every thing from the battery life to the screen brightness to how warm the device gets depends on the power management solution integrated within the device. Much of the future success of these mobile devices will depend on innovative, reliable and efficient power solutions. Perhaps this is one of the drivers behind the intense research activity seen in the power management field in recent …

Contributors
Hashim, Ahmed, Bakkaloglu, Bertan, Kiaei, Sayfe, et al.
Created Date
2013

Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based …

Contributors
Kundur, Vinay, Bakkaloglu, Bertan, Ozev, Sule, et al.
Created Date
2013

Radio frequency (RF) transceivers require a disproportionately high effort in terms of test development time, test equipment cost, and test time. The relatively high test cost stems from two contributing factors. First, RF transceivers require the measurement of a diverse set of specifications, requiring multiple test set-ups and long test times, which complicates load-board design, debug, and diagnosis. Second, high frequency operation necessitates the use of expensive equipment, resulting in higher per second test time cost compared with mixed-signal or digital circuits. Moreover, in terms of the non-recurring engineering cost, the need to measure complex specfications complicates the test development …

Contributors
Nassery, Afsaneh, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2013

The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; …

Contributors
Suh, Jounghyuk, Bakkaloglu, Bertan, Cao, Yu, et al.
Created Date
2013

In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time. Dissertation/Thesis

Contributors
Kim, Kibeom, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2013

The applications which use MEMS accelerometer have been on rise and many new fields which are using the MEMS devices have been on rise. The industry is trying to reduce the cost of production of these MEMS devices. These devices are manufactured using micromachining and the interface circuitry is manufactured using CMOS and the final product is integrated on to a single chip. Amount spent on testing of the MEMS devices make up a considerable share of the total final cost of the device. In order to save the cost and time spent on testing, researchers have been trying to …

Contributors
Jangala Naga, Naveen Sai, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2014

The research objective is fully differential op-amp with common mode feedback, which are applied in filter, band gap, Analog Digital Converter (ADC) and so on as a fundamental component in analog circuit. Having modeled various defect and analyzed corresponding probability, defect library could be built after reduced defect simulation.Based on the resolution of microscope scan tool, all these defects are categorized into four groups of defects by both function and location, bias circuit defect, first stage amplifier defect, output stage defect and common mode feedback defect, separately. Each fault result is attributed to one of these four region defects.Therefore, analog …

Contributors
Lu, Zhijian, Ozev, Sule, Kiaei, Sayfe, et al.
Created Date
2014

Mobile platforms are becoming highly heterogeneous by combining a powerful multiprocessor system-on-chip (MpSoC) with numerous resources including display, memory, power management IC (PMIC), battery and wireless modems into a compact package. Furthermore, the MpSoC itself is a heterogeneous resource that integrates many processing elements such as CPU cores, GPU, video, image, and audio processors. As a result, optimization approaches targeting mobile computing needs to consider the platform at various levels of granularity. Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. In this work, the models for …

Contributors
Gupta, Ujjwal, Ogras, Umit Y., Ozev, Sule, et al.
Created Date
2014

High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling …

Contributors
Jankunas, Benjamin, Bakkaloglu, Bertan, Kitchen, Jennifer, et al.
Created Date
2014

Modern Complex electronic system include multiple power domains and drastically varying power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are all subject to higher process variations jeopardizing stable operation of the power supply. This research mainly focus on the technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random …

Contributors
Bakliwal, Priyanka, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2015

RF transmitter manufacturers go to great extremes and expense to ensure that their product meets the RF output power requirements for which they are designed. Therefore, there is an urgent need for in-field monitoring of output power and gain to bring down the costs of RF transceiver testing and ensure product reliability. Built-in self-test (BIST) techniques can perform such monitoring without the requirement for expensive RF test equipment. In most BIST techniques, on-chip resources, such as peak detectors, power detectors, or envelope detectors are used along with frequency down conversion to analyze the output of the design under test (DUT). …

Contributors
Gangula, Sudheer Kumar Reddy, Kitchen, Jennifer, Ozev, Sule, et al.
Created Date
2015

ABSTRACT Designers creating the next generation remote sensing enabled smart devices need to overcome the challenges of prevailing ventures including time to market and expense. To reduce the time and effort involved in initial prototyping, a good reference design is often desired and warranted. This paper provides the necessary reference materials for Designers to implement a wireless solution efficiently and effectively. This document is intended for users with limited Bluetooth technology experience. Many sensing-enabled devices require a ‘hard-wire’ or cable link to a host monitoring system. This can limit the potential for product advancements by anchoring the system to a …

Contributors
Hughes, Clinton Francis, Blain Christen, Jennifer, Ozev, Sule, et al.
Created Date
2015

Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope …

Contributors
Jeong, Jae Woong, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2015

Internet of Things (IoT) has become a popular topic in industry over the recent years, which describes an ecosystem of internet-connected devices or things that enrich the everyday life by improving our productivity and efficiency. The primary components of the IoT ecosystem are hardware, software and services. While the software and services of IoT system focus on data collection and processing to make decisions, the underlying hardware is responsible for sensing the information, preprocess and transmit it to the servers. Since the IoT ecosystem is still in infancy, there is a great need for rapid prototyping platforms that would help …

Contributors
Suda, Naveen, Cao, Yu, Bakkaloglu, Bertan, et al.
Created Date
2016

Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented …

Contributors
Venkatasubramanian, Ramachandran, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2016

With the natural resources of earth depleting very fast, the natural resources of other celestial bodies are considered a potential replacement. Thus, there has been rise of space missions constantly and with it the need of more sophisticated spectrometer devices has increased. The most important requirement in such an application is low area and power consumption. To save area, some scintillators have been developed that can resolve both neutrons and gamma events rather than traditional scintillators which can do only one of these and thus, the spacecraft needs two such devices. But with this development, the requirements out of the …

Contributors
Gupta, Kush, Barnaby, Hugh, Hardgrove, Craig, et al.
Created Date
2017

Accessibility to the internal nodes of an analog/mixed-signal circuit while testing is extremely difficult. Furthermore, with technology scaling, the effect of process variations becomes more pronounced which in turn effects the test time, test cost, and die yield. As devices become more unreliable, the probability of failure of a die increases, yield decreases affecting the quality of test and cost.Therefore, test time minimization and test cost reduction are important. Moreover, process variations can affect the performance of analog/mixed circuits. Therefore, the performance of a System On-Chip(SoC) which tends to integrate multiple band gap reference circuits (BGRs) is effected due to …

Contributors
Ravouri, Yestina, Ozev, Sule, Ogras, Umit, et al.
Created Date
2017

Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST …

Contributors
Ozel, Muhlis Kenan, Bakkaloglu, Bertan, Ozev, Sule, et al.
Created Date
2017

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of …

Contributors
Beohar, Navankur, Bakkaloglu, Bertan, Ozev, Sule, et al.
Created Date
2017

Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on the devices. In this dissertation, firstly, a methodology for analyzing the performance degradation of RF circuits caused …

Contributors
Chang, Doo Hwang, Ozev, Sule, Bakkaloglu, Bertan, et al.
Created Date
2017

Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size …

Contributors
Hegde, Ashwath, Kitchen, Jennifer, Bakkaloglu, Bertan, et al.
Created Date
2018

As integrated technologies are scaling down, there is an increasing trend in the process,voltage and temperature (PVT) variations of highly integrated RF systems. Accounting for these variations during the design phase requires tremendous amount of time for prediction of RF performance and optimizing it accordingly. Thus, there is an increasing gap between the need to relax the RF performance requirements at the design phase for rapid development and the need to provide high performance and low cost RF circuits that function with PVT variations. No matter how care- fully designed, RF integrated circuits (ICs) manufactured with advanced technology nodes necessitate …

Contributors
Shafiee, Maryam, Ozev, Sule, Diaz, Rodolfo, et al.
Created Date
2018

This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal …

Contributors
EROL, OSMAN EMIR, Ozev, Sule, Kitchen, Jennifer, et al.
Created Date
2018

This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture. As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs …

Contributors
BHARDWAJ, SUMIT, Kitchen, Jennifer, Bakkaloglu, Bertan, et al.
Created Date
2018

Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has …

Contributors
Gao, Hang, Ozev, Sule, Ogras, Umit Y, et al.
Created Date
2018

Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from …

Contributors
Malakar, Pragya Priya, Kitchen, Jennifer, Ozev, Sule, et al.
Created Date
2019

With the steady advancement of neural network research, new applications are continuously emerging. As a tool for test time reduction, neural networks provide a reliable method of identifying and applying correlations in datasets to speed data processing. By leveraging the power of a deep neural net, it is possible to record the motion of an accelerometer in response to an electrical stimulus and correlate the response with a trim code to reduce the total test time for such sensors. This reduction can be achieved by replacing traditional trimming methods such as physical shaking or mathematical models with a neural net …

Contributors
Debeurre, Nicholas, Ozev, Sule, Vrudhula, Sarma, et al.
Created Date
2019

The efficiency of spacecraft’s solar cells reduces over the course of their operation. Traditionally, they are configured to extract maximum power at the end of their life and not have a system which dynamically extracts the maximum power over their entire life. This work demonstrates the benefit of dynamic re-configuration of spacecraft’s solar arrays to access the full power available from the solar panels throughout their lifetime. This dynamic re-configuration is achieved using enhancement mode GaN devices as the switches due to their low Ron and small footprint. This work discusses hardware Implementation challenges and a prototype board is designed …

Contributors
Heblikar, Anand N, Kitchen, Jennifer, Bakkaloglu, Bertan, et al.
Created Date
2019