ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
- Arunkumar, Akhil
- 1 Arizona State University
- 1 Bolotin, Evgeny
- 1 Lee, Yann-Hang
- 1 Shrivastava, Aviral
- 1 Wu, Carole-Jean
- 1 English
- 1 Public
- Computer engineering
- Computer architecture
- 1 Cache memories
- 1 Chip multiprocessors
- 1 Computer science
- 1 Graphics Processing Units
- 1 Memory subsystem
- more
- 1 Moore's law
- Dwarf Galaxies as Laboratories of Protogalaxy Physics: Canonical Star Formation Laws at Low Metallicity
- Evolutionary Genetics of CORL Proteins
- Social Skills and Executive Functioning in Children with PCDH-19
- Deep Domain Fusion for Adaptive Image Classification
- Software Defined Pulse-Doppler Radar for Over-The-Air Applications: The Joint Radar-Communications Experiment
General-purpose processors propel the advances and innovations that are the subject of humanity’s many endeavors. Catering to this demand, chip-multiprocessors (CMPs) and general-purpose graphics processing units (GPGPUs) have seen many high-performance innovations in their architectures. With these advances, the memory subsystem has become the performance- and energy-limiting aspect of CMPs and GPGPUs alike. This dissertation identifies and mitigates the key performance and energy-efficiency bottlenecks in the memory subsystem of general-purpose processors via novel, practical, microarchitecture and system-architecture solutions. Addressing the important Last Level Cache (LLC) management problem in CMPs, I observe that LLC management decisions made in isolation, as in …
- Contributors
- Arunkumar, Akhil, Wu, Carole-Jean, Shrivastava, Aviral, et al.
- Created Date
- 2018