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Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems


Abstract Performance improvements have largely followed Moore's Law due to the help from technology scaling. In order to continue improving performance, power-efficiency must be reduced. Better technology has improved power-efficiency, but this has a limit. Multi-core architectures have been shown to be an additional aid to this crusade of increased power-efficiency. Accelerators are growing in popularity as the next means of achieving power-efficient performance. Accelerators such as Intel SSE are ideal, but prove difficult to program. FPGAs, on the other hand, are less efficient due to their fine-grained reconfigurability. A middle ground is found in CGRAs, which are highly power-efficient, but largely programmable accelerators. Power-efficien... (more)
Created Date 2011
Contributor Pager, Jared (Author) / Shrivastava, Aviral (Advisor) / Gupta, Sandeep (Committee member) / Speyer, Gil (Committee member) / Arizona State University (Publisher)
Subject Computer science / Computer engineering / algorithms / CGRA / compilers / power-efficiency
Type Masters Thesis
Extent 82 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note M.S. Computer Science 2011
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis