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A Structured Design Methodology for High Performance VLSI Arrays

Abstract The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes maki... (more)
Created Date 2012
Contributor Maurya, Satendra Kumar (Author) / Clark, Lawrence T (Advisor) / Holbert, Keith (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Design / Arrayed Structures / Cache / Directed placement / Register File (RF) / Translation lookaside buffer (TLB)
Type Doctoral Dissertation
Extent 147 pages
Language English
Reuse Permissions All Rights Reserved
Note Ph.D. Electrical Engineering 2012
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis