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A 500MSPs Bipolar SiGe Track and Hold Circuit with high SFDR


Abstract The front end of almost all ADCs consists of a Sample and Hold Circuit in order to make sure a constant analog value is digitized at the end of ADC. The design of Track and Hold Circuit (THA) mainly focuses on following parameters: Input frequency, Sampling frequency, dynamic Range, hold pedestal, feed through error. This thesis will discuss the importance of these parameters of a THA to the ADCs and commonly used architectures of THA. A new architecture with SiGe HBT transistors in BiCMOS 130 nm technology is presented here. The proposed topology without complicated circuitry achieves high Spurious Free Dynamic Range(SFDR) and Total Harmonic Distortion (THD).These are important figure of merits for any THA which gives a measure of non-line... (more)
Created Date 2012
Contributor Ramakrishna Rao, Nishita Ramakrishna (Author) / Barnaby, Hugh (Advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / distortion / SFDR / THA / sample and hold
Type Masters Thesis
Extent 54 pages
Language English
Rights All Rights Reserved
Note M.S. Electrical Engineering 2012
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis