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A 1.2V 25MSPS Pipelined ADC Using Split CLS with Op-amp Sharing

Abstract ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work... (more)
Created Date 2012
Contributor Swaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Analog to Digital Converters / Pipelined Data Converters / Split Correlated Level Shifting
Type Masters Thesis
Extent 86 pages
Language English
Reuse Permissions All Rights Reserved
Note M.S. Electrical Engineering 2012
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis