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Compact Modeling of Multi-Gate Transistors

Abstract Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and ... (more)
Created Date 2012
Contributor Dessai, Gajanan (Author) / Gildenblat, Gennady (Advisor) / Gildenblat, Gennady (Committee member) / Mcandrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Subject Engineering / Electrical engineering
Type Doctoral Dissertation
Extent 138 pages
Language English
Reuse Permissions All Rights Reserved
Note Ph.D. Electrical Engineering 2012
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis