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Efficient Test Strategies for Analog/RF Circuits


Abstract Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development... (more)
Created Date 2012
Contributor Yilmaz, Ender (Author) / Ozev, Sule (Advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Adaptive Test / Analog Test / BIST EVM / Quality Aware Test
Type Doctoral Dissertation
Extent 213 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note Ph.D. Electrical Engineering 2012
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis