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System-Level Synthesis of Dataplane Subsystems for MPSoCs

Abstract In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and cus... (more)
Created Date 2013
Contributor Leary, Glenn (Author) / Chatha, Karamvir S (Advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Subject Computer science / Computer Science / Dataplane / MPSoC / Network-on-Chip / PhD / Synthesis
Type Doctoral Dissertation
Extent 172 pages
Language English
Reuse Permissions All Rights Reserved
Note Ph.D. Computer Science 2013
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis