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Compiler and Runtime for Memory Management on Software Managed Manycore Processors

Abstract We are expecting hundreds of cores per chip in the near future. However, scaling the memory architecture in manycore architectures becomes a major challenge. Cache coherence provides a single image of memory at any time in execution to all the cores, yet coherent cache architectures are believed will not scale to hundreds and thousands of cores. In addition, caches and coherence logic already take 20-50% of the total power consumption of the processor and 30-60% of die area. Therefore, a more scalable architecture is needed for manycore architectures. Software Managed Manycore (SMM) architectures emerge as a solution. They have scalable memory design in which each core has direct access to only its local scratchpad memory, and any data tran... (more)
Created Date 2014
Contributor Bai, Ke (Author) / Shrivastava, Aviral (Advisor) / Chatha, Karamvir (Committee member) / Xue, Guoliang (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Subject Computer science / Code Generation / Compiler / Manycore / Memory / Scratchpad Memory
Type Doctoral Dissertation
Extent 99 pages
Language English
Reuse Permissions All Rights Reserved
Note Ph.D. Computer Science 2014
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis