Skip to main content

Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters

Abstract Several state of the art, monitoring and control systems, such as DC motor

controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first ... (more)
Created Date 2014
Contributor Thirunakkarasu, Shankar (Author) / Bakkaloglu, Bertan (Advisor) / Garrity, Douglas (Committee member) / Kozicki, Michael (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Analog-to-digital (A/D) conversion / data converters / digital trimming / mismatch correction / self-calibration / successive approximation
Type Doctoral Dissertation
Extent 97 pages
Language English
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Electrical Engineering 2014
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

  Full Text
9.8 MB application/pdf
Download Count: 15898

Description Dissertation/Thesis