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Modeling and Simulation Tools for Aging Effects in Scaled CMOS Design

Abstract The aging process due to Bias Temperature Instability (both NBTI and PBTI) and Channel Hot Carrier (CHC) is a key limiting factor of circuit lifetime in CMOS design. Threshold voltage shift due to BTI is a strong function of stress voltage and temperature complicating stress and recovery prediction. This poses a unique challenge for long-term aging prediction for wide range of stress patterns. Traditional approaches usually resort to an average stress waveform to simplify the lifetime prediction. They are efficient, but fail to capture circuit operation, especially under dynamic voltage scaling (DVS) or in analog/mixed signal designs where the stress waveform is much more random. This work presents a suite of modelling solutions for BTI tha... (more)
Created Date 2014
Contributor Sutaria, Ketul (Author) / Cao, Yu (Advisor) / Bakkaloglu, Bertan (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Aging Effects / Bias Runaway / Channel Hot Carrier / Duty Cycle Shift under DC/AC Stress / Negative Bias Temperature Instability / Simulation Tools for Aging
Type Doctoral Dissertation
Extent 105 pages
Language English
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Electrical Engineering 2014
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis