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Compiler and Architecture Design for Coarse-Grained Programmable Accelerators

Abstract The holy grail of computer hardware across all market segments has been to sustain performance improvement at the same pace as silicon technology scales. As the technology scales and the size of transistors shrinks, the power consumption and energy usage per transistor decrease. On the other hand, the transistor density increases significantly by technology scaling. Due to technology factors, the reduction in power consumption per transistor is not sufficient to offset the increase in power consumption per unit area. Therefore, to improve performance, increasing energy-efficiency must be addressed at all design levels from circuit level to application and algorithm levels.

At architectural level, one promising approach is to populate the s... (more)
Created Date 2015
Contributor Hamzeh, Mahdi (Author) / Vrudhula, Sarma (Advisor) / Gopalakrishnan, Kailash (Committee member) / Shrivastava, Aviral (Committee member) / Wu, Carole-Jean (Committee member) / Arizona State University (Publisher)
Subject Computer science / Accelerator / Compiler / Performance
Type Doctoral Dissertation
Extent 162 pages
Language English
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Computer Science 2015
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis