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Designing Low Cost Error Correction Schemes for Improving Memory Reliability


Abstract Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power, better performance and lower hardware cost.

First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 and 3), x8 (Scheme 4) and x16 (Scheme 5) DRAM systems. All s... (more)
Created Date 2017
Contributor Chen, Hsing-Min (Author) / Chakrabarti, Chaitali (Advisor) / Mudge, Trevor (Committee member) / Wu, Carole-Jean (Committee member) / Ogras, Umit (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / Computer Architecture / Error Control Coding / Memory Reliability / Memory System
Type Doctoral Dissertation
Extent 135 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Electrical Engineering 2017
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis