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6T-SRAM 1Mb Design with Test Structures and Post Silicon Validation


Abstract Static random-access memories (SRAM) are integral part of design systems as caches and data memories that and occupy one-third of design space. The work presents an embedded low power SRAM on a triple well process that allows body-biasing control. In addition to the normal mode operation, the design is embedded with Physical Unclonable Function (PUF) [Suh07] and Sense Amplifier Test (SA Test) mode. With PUF mode structures, the fabrication and environmental mismatches in bit cells are used to generate unique identification bits. These bits are fixed and known as preferred state of an SRAM bit cell. The direct access test structure is a measurement unit for offset voltage analysis of sense amplifiers. These designs are manufactured using a f... (more)
Created Date 2017
Contributor Dosi, Ankita (Author) / Clark, Lawrence (Advisor) / Seo, Jae-sun (Committee member) / Brunhaver, John (Committee member) / Arizona State University (Publisher)
Subject Engineering
Type Masters Thesis
Extent 79 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note Masters Thesis Electrical Engineering 2017
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis