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FinFET Cell Library Design and Characterization


Abstract Modern-day integrated circuits are very capable, often containing more than a billion transistors. For example, the Intel Ivy Bridge 4C chip has about 1.2 billion transistors on a 160 mm2 die. Designing such complex circuits requires automation. Therefore, these designs are made with the help of computer aided design (CAD) tools. A major part of this custom design flow for application specific integrated circuits (ASIC) is the design of standard cell libraries. Standard cell libraries are a collection of primitives from which the automatic place and route (APR) tools can choose a collection of cells and implement the design that is being put together. To operate efficiently, the CAD tools require multiple views of each cell in the standard ... (more)
Created Date 2017
Contributor Vangala, Manoj (Author) / Clark, Lawrence T (Advisor) / Brunhaver, John S (Committee member) / Allee, David R (Committee member) / Arizona State University (Publisher)
Subject Computer engineering
Type Masters Thesis
Extent 99 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note Masters Thesis Computer Engineering 2017
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis