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Algorithm and Hardware Co-design for Learning On-a-chip

Abstract Machine learning technology has made a lot of incredible achievements in recent years. It has rivalled or exceeded human performance in many intellectual tasks including image recognition, face detection and the Go game. Many machine learning algorithms require huge amount of computation such as in multiplication of large matrices. As silicon technology has scaled to sub-14nm regime, simply scaling down the device cannot provide enough speed-up any more. New device technologies and system architectures are needed to improve the computing capacity. Designing specific hardware for machine learning is highly in demand. Efforts need to be made on a joint design and optimization of both hardware and algorithm.

For machine learning acceleration,... (more)
Created Date 2017
Contributor Xu, Zihan (Author) / Cao, Yu (Advisor) / Chakrabarti, Chaitali (Committee member) / Seo, Jae-sun (Committee member) / Yu, Shimeng (Committee member) / Arizona State University (Publisher)
Subject Electrical engineering / algorithm / hardware / machine learning
Type Doctoral Dissertation
Extent 117 pages
Language English
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Electrical Engineering 2017
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis