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Capable Copper Electrodeposition Process for Integrated Circuit - Substrate Packaging Manufacturing

Abstract This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the de... (more)
Created Date 2018
Contributor Ganesan, Kousik (Author) / Tasooji, Amaneh (Advisor) / Manepalli, Rahul (Committee member) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Subject Materials Science / Chemical engineering / Chemistry / Copper Plating / Electrodeposition / Packaging / Plating / Reverse Pulse plating / Substrate Packaging
Type Doctoral Dissertation
Extent 320 pages
Language English
Reuse Permissions All Rights Reserved
Note Doctoral Dissertation Materials Science and Engineering 2018
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis