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Memory Subsystem Optimization Techniques for Modern High-Performance General-Purpose Processors

Abstract General-purpose processors propel the advances and innovations that are the subject of humanity’s many endeavors. Catering to this demand, chip-multiprocessors (CMPs) and general-purpose graphics processing units (GPGPUs) have seen many high-performance innovations in their architectures. With these advances, the memory subsystem has become the performance- and energy-limiting aspect of CMPs and GPGPUs alike. This dissertation identifies and mitigates the key performance and energy-efficiency bottlenecks in the memory subsystem of general-purpose processors via novel, practical, microarchitecture and system-architecture solutions.

Addressing the important Last Level Cache (LLC) management problem in CMPs, I observe that LLC management deci... (more)
Created Date 2018
Contributor Arunkumar, Akhil (Author) / Wu, Carole-Jean (Advisor) / Shrivastava, Aviral (Committee member) / Lee, Yann-Hang (Committee member) / Bolotin, Evgeny (Committee member) / Arizona State University (Publisher)
Subject Computer science / Computer engineering / Cache memories / Chip multiprocessors / Computer architecture / Graphics Processing Units / Memory subsystem / Moore's law
Type Doctoral Dissertation
Extent 202 pages
Language English
Note Doctoral Dissertation Computer Science 2018
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis