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Modeling and Implementation of Threshold Logic Circuits and Architectures


Abstract Threshold logic has long been studied as a means of achieving higher performance and lower power dissipation, providing improvements by condensing simple logic gates into more complex primitives, effectively reducing gate count, pipeline depth, and number of interconnects. This work proposes a new physical implementation of threshold logic, the threshold logic latch (TLL), which overcomes the difficulties observed in previous work, particularly with respect to gate reliability in the presence of noise and process variations. Simple but effective models were created to assess the delay, power, and noise margin of TLL gates for the purpose of determining the physical parameters and assignment of input signals that achieves the lowest delay su... (more)
Created Date 2010
Contributor Leshner, Samuel (Author) / Vrudhula, Sarma (Advisor) / Chatha, Karamvir (Committee member) / Clark, Lawrence (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Subject Computer Engineering / automated design / differential logic / issue logic / modeling / multiplier / threshold logic
Type Doctoral Dissertation
Extent 204 pages
Language English
Copyright
Reuse Permissions All Rights Reserved
Note Ph.D. Computer Science 2010
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS


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Description Dissertation/Thesis