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Cost-Effective Integrated Wireless Monitoring of Wafer Cleanliness Using SOI Technology

Abstract The thesis focuses on cost-efficient integration of the electro-chemical residue sensor (ECRS), a novel sensor developed for the in situ and real-time measurement of the residual impurities left on the wafer surface and in the fine structures of patterned wafers during typical rinse processes, and wireless transponder circuitry that is based on RFID technology. The proposed technology uses only the NMOS FD-SOI transistors with amorphous silicon as active material with silicon nitride as a gate dielectric. The proposed transistor was simulated under the SILVACO ATLAS Simulation Framework. A parametric study was performed to study the impact of different gate lengths (6 μm to 56 μm), electron motilities (0.1 cm2/Vs to 1 cm2/Vs),... (more)
Created Date 2010
Contributor Pandit, Vedhas (Author) / Vermeire, Bert (Advisor) / Barnaby, Hugh (Committee member) / Chae, Junseok (Committee member) / Arizona State University (Publisher)
Subject Electrical Engineering / amorphous silicon TFT / cost effective integration / device simulation modeling / in situ contamination measurement / silvaco atlas deckbuild / SOI device design fabrication
Type Masters Thesis
Extent 91 pages
Language English
Reuse Permissions All Rights Reserved
Note M.S. Electrical Engineering 2010
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis