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Predictive Modeling for Extremely Scaled CMOS and Post Silicon Devices

Abstract To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor... (more)
Created Date 2011
Contributor Wang, Chi-Chao (Author) / Cao, Yu (Advisor) / Chakrabarti, Chaitali (Committee member) / Clark, Lawrence (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Subject Electrical Engineering / Fe-FET / Layout dependent stress effect / nano CMOS / Predictive Modeling / Through Silicon Via
Type Doctoral Dissertation
Extent 110 pages
Language English
Reuse Permissions All Rights Reserved
Note Ph.D. Electrical Engineering 2011
Collaborating Institutions Graduate College / ASU Library
Additional Formats MODS / OAI Dublin Core / RIS

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Description Dissertation/Thesis